Identification of Dynamic Performance, Power, and Resource Management in Chip of Multiprocessors

• Author(s): Priya Mishra
• Paper ID: 1703694
• Page: 543-548
• Published Date: 23-07-2022
• Published In: Iconic Research And Engineering Journals
• Publisher: IRE Journals
• e-ISSN: 2456-8880
• Volume/Issue: Volume 6 Issue 1 July-2022

Abstract

Multicore CPUs are currently supported by all modern electronic gadgets. Power management, on the other hand, is one of the most important aspects of today's microprocessor architecture. The purpose of power management is to get the most out of a limited amount of energy. Power management strategies must strike a compromise between the pressing requirement for better performance/throughput and the negative thermal impacts of aggressive power usage. This study involves into the fundamentals of multicore processors, as well as current research topics in the field, before focusing on power management concerns in multicore architectures. This paper's main goal is to survey and explain existing power management approaches. Microprocessor performance has risen at an exponential rate in recent years. Parallelism has been achieved via a variety of techniques, including pipelining, super- scalar architectures, and chip multiprocessors or multicore processors. We discuss the many degrees of parallelism and how subsequent technologies attempted to leverage each level in this paper. Reactive and predictive power management strategies are the two primary kinds of developed power management techniques. The technique reacts to changes in workload performance in reactive approaches. In other words, a workload may contain phases that need high performance, as well as ones that require I/O delays and poor performance. When the workload status changes, the method adjusts to the new situation. Predictive approaches, on the other hand, can help to solve this problem. Those strategies detect workload phase changes before they occur, allowing them to intervene quickly before a program's phase changes. As a consequence, you get the best energy saving and performance outcomes.

Keywords

Multi-core Architecture, Parallelism, Super-Scalar Architecture, Reactive and Predictive Power Management

Citations

IRE Journals:
Priya Mishra "Identification of Dynamic Performance, Power, and Resource Management in Chip of Multiprocessors" Iconic Research And Engineering Journals Volume 6 Issue 1 2022 Page 543-548

IEEE:
Priya Mishra "Identification of Dynamic Performance, Power, and Resource Management in Chip of Multiprocessors" Iconic Research And Engineering Journals, 6(1)