Design of Fault Tolerance Parallel FFT’s Using Xilinx 14.5v

• Author(s): N. Raj Kumar ; Kamble Shivadayal
• Paper ID: 1703175
• Page: 1-6
• Published Date: 01-02-2022
• Published In: Iconic Research And Engineering Journals
• Publisher: IRE Journals
• e-ISSN: 2456-8880
• Volume/Issue: Volume 5 Issue 8 February-2022

Abstract

Soft errors stance a dependability threat to modern-day electronic circuits. This makes defense against soft errors a requirement for several applications. Communications along with signal handling systems are no exemptions to this pattern. To maintain the reliability of the complex systems few techniques have been proposed. For some applications, a remarkable option is to utilize algorithmic based blunder resistance (ABFT) methods that attempt to exploit the algorithmic household or business homes to identify as well as proper errors. Signal handling along with communication applications are well matched for ABFT. One circumstance is Fast Fourier Transforms (FFTs) that are a key structure in many systems. There are various protection schemes to identify and adjust errors in FFTs. It is normal to discover various blocks are working in parallel. Recently; a new method is exploiting to implement a blame tolerance in parallel. In this brief, this technique is first applied to protect FFTs. Then, two improved protection schemes that combine the use of error correction codes and Parseval checks are proposed and evaluated. The results show that the proposed schemes can further reduce the implementation cost of protection.

Keywords

Error correction codes (ECCs), Fast Fourier Transforms (FFTs), soft errors.

Citations

IRE Journals:
N. Raj Kumar , Kamble Shivadayal "Design of Fault Tolerance Parallel FFT’s Using Xilinx 14.5v" Iconic Research And Engineering Journals Volume 5 Issue 8 2022 Page 1-6

IEEE:
N. Raj Kumar , Kamble Shivadayal "Design of Fault Tolerance Parallel FFT’s Using Xilinx 14.5v" Iconic Research And Engineering Journals, 5(8)