In this paper an area and power efficient design of 8 bit Carry Select Adder (CSLA) has been proposed. Conventional and other CSLAs are designed using CMOS technology, which has complexity in terms of area and power consumption. So to overcome this problem a new technology is implemented on the CSLA. This paper shows the implementation and comparison of Carry Select Adder (CSA) using BEC (Binary Excess one Converter) and First Zero Finding (FZF) logic implementation techniques with optimization of GDI Logic by minimize number of transistors. All the designs are implemented 1.8 Volt power supply and 180 nm technology in Cadence Virtuoso environment.
Carry Select Adder (CSLA); GDI (Gate Diffusion Input); RCA (Ripple Carry Adder); MUX (Multiplexer); BEC (Binary to Excess one Convertor); FZF(First Zero Finding
SANGEETHA K , KAYALVIZHI S "AREA AND POWER EFFICIENCY OF CARRY SELECT ADDER USING GATE DIFFUSION INPUT(GDI) LOGIC" Iconic Research And Engineering Journals Volume 3 Issue 1 2019 Page 143-147
SANGEETHA K , KAYALVIZHI S "AREA AND POWER EFFICIENCY OF CARRY SELECT ADDER USING GATE DIFFUSION INPUT(GDI) LOGIC" Iconic Research And Engineering Journals, 3(1)