DESIGN AND ANALYSIS OF LOW POWER WALLACE TREE MULTIPLIER

• Author(s): R. RAJ ; M. NAVANEETHA VELAMMAL
• Paper ID: 1701228
• Page: 73-78
• Published Date: 14-05-2019
• Published In: Iconic Research And Engineering Journals
• Publisher: IRE Journals
• e-ISSN: 2456-8880
• Volume/Issue: Volume 2 Issue 11 May-2019

Abstract

In this project, a new binary counter design is proposed. It uses 3-bit stacking circuits, which group all of the ?1? bits together, followed by a novel symmetric method to combine pairs of 3-bit stacks into 6-bit stacks. The bit stacks are then converted to binary counts, producing 6:3 counter circuits with no XOR gates on the critical path. This avoidance of XOR gates results in faster designs with efficient power and area utilization. In VLSI simulations, the proposed counters are 30% faster than existing parallel counters and also consume less power than other higher order counters. Using the new counter design Wallace tree multiplier was produced. Wallace tree multiplier will be designed of multiplication of n-bits should be used .Based on that the Wallace tree multiplier architecture has been proposed. The proposed multiplier utilized the maximum combination path delay of 27.711ns. This multiplier has also been designed by using cadence tool to view the less number of transistors usage. In turn the minimum power was required

Keywords

counter, stacks, Wallace tree multiplier

Citations

IRE Journals:
R. RAJ , M. NAVANEETHA VELAMMAL "DESIGN AND ANALYSIS OF LOW POWER WALLACE TREE MULTIPLIER" Iconic Research And Engineering Journals Volume 2 Issue 11 2019 Page 73-78

IEEE:
R. RAJ , M. NAVANEETHA VELAMMAL "DESIGN AND ANALYSIS OF LOW POWER WALLACE TREE MULTIPLIER" Iconic Research And Engineering Journals, 2(11)