LOW POWER FULL SWING SRAM ARCHITECTURE WITH POWER GATING

• Author(s): A.Ashna ; M.Farous Khan ; T.G.Karthikeyan ; R.Arun Raj
• Paper ID: 1701151
• Page: 225-229
• Published Date: 03-05-2019
• Published In: Iconic Research And Engineering Journals
• Publisher: IRE Journals
• e-ISSN: 2456-8880
• Volume/Issue: Volume 2 Issue 10 April-2019

Abstract

The attacks in the field of power analysis is becoming a major threat to security systems by triggering secret data extraction using side channel leakage information .Nowadays almost every Memory in Embedded systems, is now utilizing 8T and 6T SRAM cells, it is one of the major components in many systems .Generally SRAM cells are likely to suffer from side channel leakage power attacks .To overcome this types of attacks, we proposed a 9T SRAM which has one additional transistor compared to 8T cell and incorporates three more transistor when compared to 6T SRAM cell which greatly improves the number of operations per second in SRAM interms of speed and the power is also decreased The cells were implemented in 125nm technology on Tanner EDA tool.

Keywords

Static Random Access Memory (SRAM), Side Channel Attacks (SCA), Leakage Power Analysis (LPA)

Citations

IRE Journals:
A.Ashna , M.Farous Khan , T.G.Karthikeyan , R.Arun Raj "LOW POWER FULL SWING SRAM ARCHITECTURE WITH POWER GATING" Iconic Research And Engineering Journals Volume 2 Issue 10 2019 Page 225-229

IEEE:
A.Ashna , M.Farous Khan , T.G.Karthikeyan , R.Arun Raj "LOW POWER FULL SWING SRAM ARCHITECTURE WITH POWER GATING" Iconic Research And Engineering Journals, 2(10)