Design And Implementation Of Low-Complexity Redundant Multiplier Architecture For Finite Field
Abstract
In the present work, a low-complexity Digit-Serial/parallel Multiplier over Finite Field is proposed. It is employed in applications like cryptography for data encryption and decryption to deal with discrete mathematical and arithmetic structures. The proposed multiplier utilizes a redundant representation because of their free squaring and modular reduction. The proposed 10-bit multiplier is simulated and synthesized using Xilinx Verilog HDL. It is evident from the simulation results that the multiplier has significantly low area and power when compared to the previous structures using the same representation.
Keywords
Digit-Serial, Finite Field multiplication, Redundant Basis
Citations
IRE Journals:
VEERRAJU KAKI
"Design And Implementation Of Low-Complexity Redundant Multiplier Architecture For Finite Field" Iconic Research And Engineering Journals Volume 1 Issue 6 2017 Page 76-80
IEEE:
VEERRAJU KAKI
"Design And Implementation Of Low-Complexity Redundant Multiplier Architecture For Finite Field" Iconic Research And Engineering Journals, 1(6)
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